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PIC18F1230/1330

DS39758D-page 174

2009 Microchip Technology Inc.

16.1

Triggering A/D Conversions

The A/D conversion can be triggered by setting the GO/

DONE bit. This bit can either be set manually by the

programmer or by setting the SEVTEN bit of ADCON0.

When the SEVTEN bit is set, the Special Event Trigger

from the Power Control PWM module triggers the A/D

conversion. For more information, see Section 14.14

“PWM Special Event Trigger”

16.2

A/D Acquisition Requirements

For the A/D Converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 16-3. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 k

. After the analog input channel is

selected (changed), the channel must be sampled for

at least the minimum acquisition time before starting a

conversion.

calculate

the

minimum

acquisition

time,

Equation 16-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

Example 16-3 shows the calculation of the minimum

required acquisition time, TACQ. This calculation is

based

the

following

application

system

assumptions:

CHOLD

=25 pF

2.5 k

Conversion Error

1/2 LSb

VDD

=5V

RSS = 2 k

Temperature

C (system max.)

EQUATION 16-1:

ACQUISITION TIME

EQUATION 16-2:

A/D MINIMUM CHARGING TIME

EQUATION 16-3:

CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

Note:

When the conversion is started, the

holding capacitor is disconnected from the

input pin.

TACQ

Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

=TAMP + TC + TCOFF

VHOLD

(VREF – (VREF/2048)) (1 – e(-T

/CHOLD(RIC + RSS + RS)))

-(CHOLD)(RIC + RSS + RS) ln(1/2048)

TACQ

=TAMP + TC + TCOFF

TAMP

=0.2

TCOFF

(Temp – 25

C)(0.02 s/C)

(85

C – 25C)(0.02 s/C)

1.2

Temperature coefficient is only required for temperatures > 25

C. Below 25C, TCOFF = 0 ms.

-(CHOLD)(RIC + RSS + RS) ln(1/2047)

-(25 pF) (1 k

+ 2 k + 2.5 k) ln(0.0004883)

1.05

TACQ

=0.2

s + 1 s + 1.2 s

2.4

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